AI-assisted development with AMD Vitis HLS

Name: AI-assisted development with AMD Vitis HLS
Start: 2026-08-06
End: 2026-08-06

OnlineCompletedWebinar

FPGA

MCP, reusable skills and optimization case studies for FPGA design.

Recording

1 found

RecordingAccess not confirmed
Webinar recording
en
Source: webinar.amd.com

Materials checked: Oct 8, 2026

The programme examines microarchitecture choices and pragma tuning. It describes how design knowledge and established HLS methods can be supplied to language models.

Oct 12 – 15, 2026 United States · San Jose

OCP Global Summit 2026

Open infrastructure sessions and Lattice–AMI demonstrations of platform firmware, management and control technologies.

In person

Oct 16, 2026 Japan · Yokohama

FPGA Development and FPGA AI Suite Hands-on with Agilex 3 and Agilex 5

AI inference with FPGA AI Suite, handwritten-digit recognition on Terasic Atum A3 Nano, and an Agilex 5 demonstration.

In person FPGA

Recording

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