Verifying an OpenRAN radio unit on AMD RFSoC DFE

Name: Verifying an OpenRAN radio unit on AMD RFSoC DFE
Start: 2026-09-29
End: 2026-09-29

OnlineCompletedWebinar

FPGA

MATLAB modelling and RTL comparison for the Zynq UltraScale+ O-RU reference design.

Recording

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Webinar recording
en
Source: webinar.amd.com

Materials checked: Oct 8, 2026

The programme includes a digital twin, self-checking downlink and uplink simulation, and an O-RAN demonstration. It addresses validation of custom additions to the radio design.

Oct 12 – 15, 2026 United States · San Jose

OCP Global Summit 2026

Open infrastructure sessions and Lattice–AMI demonstrations of platform firmware, management and control technologies.

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Oct 16, 2026 Japan · Yokohama

FPGA Development and FPGA AI Suite Hands-on with Agilex 3 and Agilex 5

AI inference with FPGA AI Suite, handwritten-digit recognition on Terasic Atum A3 Nano, and an Agilex 5 demonstration.

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