FOSDEM 2025: Open-Source CPU: Deep-dive into RISC-V CFU and Zephyr

Name: FOSDEM 2025: Open-Source CPU: Deep-dive into RISC-V CFU and Zephyr
Start: 2025-02-01T16:20:00.000Z
End: 2025-02-01T16:55:00.000Z

FPGA

Connecting custom RISC-V hardware functions with Zephyr in an FPGA-based system.

Materials

2 found

Materials checked: Oct 8, 2026

Mohammed Billoo presented this session in the RISC-V track. The official archive links the recording and presentation slides.

Oct 12 – 15, 2026 United States · San Jose

Open infrastructure sessions and Lattice–AMI demonstrations of platform firmware, management and control technologies.

Oct 28, 2026, 08:00–17:30 United States · San Jose

Sessions on Agilex, Quartus synthesis and timing, SoC development and FPGA–GPU sensor processing.