Materials
34 found
- DocumentSchool introduction and programmeSource: fpga-ignite.github.io
- SlidesAccess not confirmedFOSSi Foundation and open-source chip designSource: fpga-ignite.github.io
- DocumentCocotb laboratory exercisesSource: fpga-ignite.github.io
- SlidesAccess not confirmedReconfigurable RISC-V extensions with FABulous eFPGAsSource: fpga-ignite.github.io
- DocumentFABulous eFPGA hands-on tutorialSource: fpga-ignite.github.io
- SlidesAccess not confirmedRISC-V fine-grain multithreading and custom instructionsSource: fpga-ignite.github.io
- SlidesAccess not confirmedOpenLane introductionSource: fpga-ignite.github.io
- DocumentOpenLane tutorial: hardening macrosSource: fpga-ignite.github.io
- DocumentOpenLane tutorial: hardening the coreSource: fpga-ignite.github.io
- ReportFPGA Ignite 2024: host reportSource: www.ziti.uni-heidelberg.de
- DocumentAccess not confirmedEnergy-Efficient Deep Learning Accelerators with Workload Awareness for Embedded FPGAs
Chao Qian and Professor Gregor Schiele
Source: fpga-ignite.github.io - DocumentAccess not confirmedFazyRV - A Scalable RISC-V Core
Meinhard Kissich and Marcel Baunach
Source: fpga-ignite.github.io - DocumentAccess not confirmedPre-Silicon Formal Verification and Post-Silicon Assertion Checker on RISC-V Processor
Czea Sie Chuah
Source: fpga-ignite.github.io - DocumentAccess not confirmedNovel True Random Number Generator (TRNG) Modules on Different FPGA Platforms
Dr. Hossam O. Ahmed
Source: fpga-ignite.github.io - DocumentAccess not confirmedGraph Neural Networks Acceleration with Adaptive Dataflow Architectures & FPGA
Zheyu Liu, Christos Kotselidis
Source: fpga-ignite.github.io - DocumentAccess not confirmedRISC-V Opt-VP: An Application Analysis Platform Using Bounded Execution Trees
Jan Zielasko(1,2), Rune Krauss(1), Rolf Drechsler
Source: fpga-ignite.github.io - DocumentAccess not confirmedApproximate Tiny Machine Learning on Lightweight FPGAs
Georgios Mentzos, Prof. Jörg Henkel
Source: fpga-ignite.github.io - DocumentAccess not confirmedApproximate Logic Synthesis via Iterative SMT-based Subcircuit Rewriting and Through a Prametrizable FPGA or ASIC Template
Morteza Rezaalipour(1), Marco Biasion(1), Cristian Tirelli(1), Mohammad Atwi(1), Cristian Tirelli(1), Lorenzo Ferretti(2), Rodrigo Otoni(1), Professor. George A. Constantinides(3), Laura Pozzi(1)
Source: fpga-ignite.github.io - DocumentAccess not confirmedResilient Processing Platform for 6G Mobile Networks
M. Andjelkovic, J. Chen, R. T. Syed, F. Vargas, M. Ulbricht
Source: fpga-ignite.github.io - DocumentAccess not confirmedTo Clock or not to Clock: Clock Gate Insertion with a Yosys-based Netlist Modification Tool
Manuel Jirsak, Adrian Pitterling, Jonas Lienke, Georg Gläser
Source: fpga-ignite.github.io
Materials checked:
ZITI’s retrospective reports 60 in-person and 80 online participants. Lectures and labs were followed by a two-day hackathon; those figures describe the host’s report.