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Improving Fmax with Hyper Register on Agilex 3

Hyperflex architecture, Quartus Prime Pro design flow and a practical exercise with Hyper Register.

Macnica logo, organizer of the FPGA practical session
Macnica — official event page

Programme

The agenda covers Agilex 3, Hyperflex core architecture, Quartus Prime Pro Edition and the fundamentals of high-speed design. It includes Fast Forward Timing Closure Recommendations and an exercise on Fmax using Hyper Register.

The audience includes engineers interested in Agilex 3 performance and newcomers to FPGA development or Hyperflex. The organizer notes that some programme content may change.

Oct 12 – 15, 2026 United States · San Jose

OCP Global Summit 2026

Open infrastructure sessions and Lattice–AMI demonstrations of platform firmware, management and control technologies.