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YADRO ASIC+RTL+FPGA MEETUP: from verification to test launch

HybridCompleted
Verilog / SystemVerilogFPGA + SoCFPGA

A hybrid YADRO meetup covered SoC verification, iterative FPGA builds, automated test infrastructure, UVM, Cocotb, PyUVM and FPGA prototyping clusters.

Illustration for the YADRO ASIC+RTL+FPGA meeting in Minsk
Image: YADRO. Official source.

Programme

The programme targeted FPGA, ASIC and RTL engineers. Talks covered the SoC verification software lifecycle, iterative FPGA project builds, and a test-reservation system for a laboratory with 500 boards and several million tests.

Further sessions addressed the full functional-verification route, including UVM, Cocotb and PyUVM, FPGA clusters for prototyping and verification, and a panel on open design and verification flows under proprietary-tool restrictions.

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