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Engineering Systems: RISC-V & FPGA — Nizhny Novgorod, 2026

Hybrid
Verilog / SystemVerilogFPGA + SoCRISC-VOpen-source

14 November at Lobachevsky University and online: RISC-V modelling, SoC benchmarking on FPGA, FFT architectures, JTAG, Verihogg and FPGA optimisation.

Illustration for Engineering Systems: RISC-V & FPGA
Image: YADRO. Official source.

Programme

The morning RISC-V programme covers adapting gem5 for processor development, QEMU SoC modelling and vector maths libraries. Registration opens at 09:30; the opening session starts at 10:40.

FPGA-Systems talks start at 16:00, with registration from 15:00 to 16:00. Topics include processor benchmarking on FPGA, FFT architectures, shared JTAG for FPGA and RISC-V, Verihogg and architecture-specific FPGA optimisation.

FPGA talks end at 20:00; networking and exhibits end at 21:00. Organised by YADRO, the programme brings together the RISC-V Alliance and FPGA-Systems meetings.

Attendance

Attendance is free and requires registration on the organiser’s website. Select online attendance to receive the stream link. University tours require separate booking and have limited capacity. Check the programme before travelling.

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