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YADRO SoC Design Challenge 2022

In personCompleted
Verilog / SystemVerilogFPGA + SoCEducationRISC-V

Archive of the 2022 YADRO and MIET engineering hackathon in Zelenograd: practical digital-design and verification tasks.

YADRO SoC Design Challenge 2022: photograph from MIET
Image: НИУ МИЭТ / MIET. Official source.

Hackathon tasks

Three tracks: RTL design, functional verification and physical design. Student teams solved practical tasks with YADRO mentors.

Organised by YADRO and MIET. This in-person Zelenograd edition has ended and its registration is closed.

Materials

Official event page and programme

Independent preparation

Use the track descriptions to guide RTL practice, verification planning and synthesis-report review. Selection rules from a past edition do not establish the rules for a future hackathon.

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