Hackathon tasks
Four tracks: RTL design, UVM verification, SoC system verification and physical design, with BASIC and BASIC+ levels.
Organised by YADRO and MIET. This in-person Zelenograd edition has ended and its registration is closed.
Materials
Official event page and programme
Independent preparation
Use the track descriptions to guide RTL practice, verification planning and synthesis-report review. Selection rules from a past edition do not establish the rules for a future hackathon.