Hackathon tasks
Five tracks: physical design, UVM verification, system verification, RTL design and DFT structures. Tasks focused on SoC and RISC-V processor development.
Organised by YADRO and MIET. The in-person Zelenograd edition was scheduled for 24–26 April 2026; those calendar dates have passed and registration is closed. The official page retains its programme.
Materials
Official event page and programme
Independent preparation
Use the track descriptions to guide RTL practice, verification planning and synthesis-report review. Selection rules from a past edition do not establish the rules for a future hackathon.