FPGA-Systems 2024.02 × YADRO — Moscow
Programme, recording and slides from 30 November 2024: Chisel/Scala, UVM, RISC-V, verification, timing and HDMI on FPGA.
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FPGA-Systems 2024.02 × YADRO — Saint Petersburg
Recording and slides from 26 October 2024: FPGA and ASIC physical design, embedded Linux, prototyping, PyUVM and Simtera.
FPGA Ignite Summer School 2024
Cocotb, RISC-V customisation, FABulous embedded FPGA and an open-tool chip-design hackathon.
FPGA Developers' Forum 2024
Implementation methods, tool flows and FPGA applications in physics and other engineering fields.
FPGA-Systems 2024.1 with YADRO — Moscow
Recording and slides from the 1 June 2024 conference: SATA on FPGA, AVC/H.264, industrial automation, Simtera and RISC-V.
FPGA-Systems 2024.1 with YADRO — Saint Petersburg
Recording and slides from 25 May 2024: a DDC/DUC transceiver, verification strategy, trusted boot, PyUVM and reusable RTL verification components.
YADRO ASIC+RTL+FPGA: Minsk meeting, 2 March 2024
Recording and slides on SoC verification, iterative FPGA builds, automated board testing and FPGA clusters.
FOSDEM 2024: Maia SDR: an open-source FPGA-based project for AD936x+Zynq radios
Maia SDR uses Amaranth gateware for AD936x/Zynq radios; the talk covers signal processing and IQ data capture.
FOSDEM 2024: Zephyr and RISC-V: I Ain't Afraid Of No Ghosts
Running Zephyr on an FPGA-hosted RISC-V core on UPduino and connecting the embedded hardware resources.
FOSDEM 2024: Libre-SOC, FPGA and VLSI devroom
5 sessions on open hardware design, FPGA tooling and related silicon projects.