FPGA-Systems 2024.02 × YADRO — Moscow
Programme, recording and slides from 30 November 2024: Chisel/Scala, UVM, RISC-V, verification, timing and HDMI on FPGA.
3 events
Programme, recording and slides from 30 November 2024: Chisel/Scala, UVM, RISC-V, verification, timing and HDMI on FPGA.
Recording and slides from 26 October 2024: FPGA and ASIC physical design, embedded Linux, prototyping, PyUVM and Simtera.
A hybrid YADRO meetup covered SoC verification, iterative FPGA builds, automated test infrastructure, UVM, Cocotb, PyUVM and FPGA prototyping clusters…