AMD Spartan UltraScale+ FPGA architecture
I/O density, power and security in the cost-optimized device family.
147 events
I/O density, power and security in the cost-optimized device family.
Processor features, configuration and integration with Vivado and Vitis.
Security at the intelligent edge.
Sensor connectivity, deterministic dataflow and AI inference.
Code profiling and implementation examples in the unified design flow.
Hardware choices for ML software development.
Cooling and power constraints in medical systems.
High-speed image-sensor interfaces with FPGA processing.
Programmable logic for industrial systems.
Power-aware communications design.