Compiler directives for AMD Vitis HLS
Exploring hardware architectures from the same C/C++ model.
FPGA events
Add event147 events
EagleCore PolarFire SoC SOM: Mighty Power in a Compact Form
A Numato Lab system-on-module with a RISC-V processor and FPGA fabric.
Unleash the Power of the Linux-Enabled IoT H.264 Camera with PolarFire SoC
FPGA video compression with processor-side Linux software.
Post-Quantum Protection on Intelligent Edge SoCs
Secure boot and cryptography for PolarFire SoC.
Declutter Your Code and Get in the Lab Faster With SmartHLS Compiler Software
Describing FPGA accelerators in a high-level language.
Kria KD240 motor-control design with MATLAB and Simulink
Model-based design and field-oriented control with the K24 module.
AMD Kria K24 and the KD240 Drives Starter Kit
Motor control, DSP and development flows for the adaptive system-on-module.
Vitis developer series: AI Engine design in 2023
DSP libraries, Model Composer, test harnesses and system integration.
OPC Unified Architecture (OPC UA) in Industrial Edge With PolarFire SoC FPGAs
Industrial communications on a RISC-V SoC FPGA.
Facial recognition and licence-plate reading with VectorBlox on PolarFire FPGAs
Multiple CNNs deployed on PolarFire FPGAs.