FOSDEM 2025: All Open Source Toolchain for ZYNQ 7000 SoCs
GenZ generates processing-system configuration while OpenXC7 builds the programmable logic for Zynq-7000.
24 events
GenZ generates processing-system configuration while OpenXC7 builds the programmable logic for Zynq-7000.
A CubeSat communications subsystem combining STM32H743 control with a Zynq-7020 accelerator and open hardware.
Maia SDR uses Amaranth gateware for AD936x/Zynq radios; the talk covers signal processing and IQ data capture.
Running Zephyr on an FPGA-hosted RISC-V core on UPduino and connecting the embedded hardware resources.
5 sessions on open hardware design, FPGA tooling and related silicon projects.
A 64-bit RISC-V FPGA computer running Fedora and rebuilding its software and FPGA bitstream from source.
Yosys, nextpnr and LiteX for ECP5 systems with a soft RISC-V processor.
The eurorack-pmod module and an open-tool workflow for FPGA-based music hardware.
Archive of the YADRO and Sirius University workshop on 3 October 2022: FPGA programming, RISC-V and SoC development at Microelectronics 2022.
A PCIe data path between an SDR and a GPU, using Artix FPGA gateware with LiteX and host software in Julia.