Performance pragmas in AMD Vitis HLS
Translating throughput targets into synthesis constraints.
FPGA events
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AMD Alveo V80: AVED and partner implementations
Reference design, low-latency AI inference and FPGA networking.
AMD Versal design tools and architecture: webinar series
Power, thermal design, NoC, transceivers, processors and embedded software.
AMD Versal AI Engine development: webinar series
Architecture, system integration, Model Composer and DSP examples.
RF spectrum processing with Mercury RFS1140
A system-in-package combining AMD Versal AI Core and Jariet data converters.
AMD Vitis HLS execution modes
Sequential, pipelined and continuously running hardware modules.
Meeting Fmax targets with AMD Vivado and Versal
Clocking architecture, calibrated deskew and the Advanced Flow.
MUSIC signal processing on AMD Versal AI Engines
Hardware acceleration for direction-of-arrival and spectral estimation.
AMD cost-optimized FPGAs: device selection and design
A five-session series on interfaces, power, tools, IP and security.
Exporting AMD Vitis designs to Vivado
Vitis Metadata Archive files and the hardware–software handoff.