AMD Spartan UltraScale+ FPGAs: Japanese session
I/O, power, security and the cost-optimized device portfolio.
FPGA events
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AMD cost-optimized FPGAs: device and tool comparisons
Resource use, performance, power, thermal design and timing closure.
CXL on AMD Versal Premium Series Gen 2
The memory subsystem and memory-centric acceleration use cases.
Automotive AI and functional safety with AMD Versal
Versal AI Edge Series Gen 2 for inference and automotive post-processing.
Migrating to AMD Vitis Unified IDE: two-part series
IDE migration, system device trees, Lopper and legacy drivers.
AMD Alveo V80 for memory-intensive workloads
Versal HBM acceleration and the AVED design flow for RTL developers.
M_AXI interfaces in AMD Vitis HLS
Connecting HLS-generated hardware to external memory.
AMD Versal AI Engines for DSP: webinar series
Architecture, polyphase channelizers and FFT implementation on AIE-ML.
AMD Spartan UltraScale+ FPGA architecture
I/O density, power and security in the cost-optimized device family.
AMD MicroBlaze V: RISC-V soft processor
Processor features, configuration and integration with Vivado and Vitis.