Verifying an OpenRAN radio unit on AMD RFSoC DFE
MATLAB modelling and RTL comparison for the Zynq UltraScale+ O-RU reference design.
FPGA events
Add event15 events
Routing 0.5 mm FPGA packages without HDI
PCB design with FR4 and through-hole vias for AMD Artix UltraScale+.
Polyphase channelizer optimization on AMD Versal AI Engines
Compute, memory and I/O partitioning with Vitis Libraries.
AMD Kria and Ryzen AI platforms for autonomous robots
Kria AI modules, the robotics development platform and software tools.
Embedded debugging with AMD Vitis Unified IDE
Memory inspection, PS–PL cross triggering and crash analysis.
AMD Spartan UltraScale+ FPGAs in servers and switches
Boot, security, monitoring and connectivity for data-center infrastructure.
AI-assisted development with AMD Vitis HLS
MCP, reusable skills and optimization case studies for FPGA design.
Vitis subsystem simulation with hardware-in-the-loop and Python
A webinar on combining simulation with hardware execution.
Designing with 0.5 mm AMD FPGA packages
PCB design for devices with a fine ball-grid pitch.
DSP algorithms in hardware with AMD Vitis HLS
High-level synthesis for digital signal processing.