FOSDEM 2024: Maia SDR: an open-source FPGA-based project for AD936x+Zynq radios
Maia SDR uses Amaranth gateware for AD936x/Zynq radios; the talk covers signal processing and IQ data capture.
21 events
Maia SDR uses Amaranth gateware for AD936x/Zynq radios; the talk covers signal processing and IQ data capture.
Running Zephyr on an FPGA-hosted RISC-V core on UPduino and connecting the embedded hardware resources.
5 sessions on open hardware design, FPGA tooling and related silicon projects.
A 64-bit RISC-V FPGA computer running Fedora and rebuilding its software and FPGA bitstream from source.
Yosys, nextpnr and LiteX for ECP5 systems with a soft RISC-V processor.
The eurorack-pmod module and an open-tool workflow for FPGA-based music hardware.
A PCIe data path between an SDR and a GPU, using Artix FPGA gateware with LiteX and host software in Julia.
Integration of GNU Radio with LiteX on an Acorn CLE-215+ PCIe FPGA card for hardware signal processing.
An update on openwifi features, hardware support and development plans following its 2021 work.
7 sessions on open hardware design, FPGA tooling and related silicon projects.