YADRO FPGA community meetup 2026
Recording of the 26 May 2026 meetup: yosys-slang, SystemRDL, register documentation, Edge AI on FPGA and AI-assisted waveform analysis.
13 events
Recording of the 26 May 2026 meetup: yosys-slang, SystemRDL, register documentation, Edge AI on FPGA and AI-assisted waveform analysis.
Recordings from both rooms of the 29 November 2025 conference: RTL, DSP, PCIe prototyping, FPGA-to-ASIC design, verification and physical implementati…
Programme, recording and slides from 30 November 2024: Chisel/Scala, UVM, RISC-V, verification, timing and HDMI on FPGA.
Recording and slides from 26 October 2024: FPGA and ASIC physical design, embedded Linux, prototyping, PyUVM and Simtera.
Recording and slides from the 1 June 2024 conference: SATA on FPGA, AVC/H.264, industrial automation, Simtera and RISC-V.
Recording and slides from 25 May 2024: a DDC/DUC transceiver, verification strategy, trusted boot, PyUVM and reusable RTL verification components.
Recording of the 9 December 2023 conference: SystemVerilog/VHDL in Quartus and Vivado, SpaceWire, SD cards, Simtera, multiply-add and Drawio HDL Build…
Recording of the 2 December 2023 conference: virtual FPGA labs, QEMU, Simtera, digital predistortion, chip prototypes and iterative builds.
25 November 2023 at MIEM and online: LiteX, FPGA bench automation, virtual FPGA, SystemRDL and UVM for DSP. Recording available.
Recording of the 8 April 2023 conference: open synthesis tools, remote FPGA access, Pangomicro, FPGA clusters, DEEDS and timing analysis.