Latch-Up 2025
North American open hardware meeting with FPGA, verification and open EDA sessions.
FPGA events
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AMD Vitis HLS execution modes
Sequential, pipelined and continuously running hardware modules.
Lattice security trends seminar 2025
AI, post-quantum cryptography, CRA and programmable hardware security.
FPGA hardware integration into processing systems (French session)
A French-language session on integrating FPGA hardware into a processing system.
FPGA hardware integration into processing systems (Polish session)
A Polish-language session on integrating FPGA hardware into a processing system.
Meeting Fmax targets with AMD Vivado and Versal
Clocking architecture, calibrated deskew and the Advanced Flow.
FPGA hardware integration into processing systems (German session)
A German-language session on integrating FPGA hardware into a processing system.
Understanding Hart Software Services (HSS) on the PolarFire SoC FPGAs
HSS firmware in PolarFire SoC applications.
Master FPGA Debugging With SmartDebug: the Secret Weapon for Lightning-Fast FPGA Debugging
Hardware inspection and debugging with Microchip SmartDebug.
MUSIC signal processing on AMD Versal AI Engines
Hardware acceleration for direction-of-arrival and spectral estimation.