Vivado design flow for Spartan UltraScale+ FPGAs
Design iterations, timing closure and available IP blocks.
FPGA events
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Introducing PolarFire SoC Core Family
The PolarFire SoC Core device family and its development resources.
Catapult HLS: AI design exploration on Lattice FPGA
Lattice and Siemens explore SoftMax implementations, resource use and performance trade-offs.
VectorBlox FPGA acceleration and NVIDIA Holoscan integration
Combining FPGA inference with a heterogeneous edge-AI platform.
FPGA Horizons London 2025
FPGA engineering talks on device architectures, design tools and applied development.
Vitis functional simulation with MATLAB
Calling AI Engine graphs and Vitis HLS programmable-logic kernels from MATLAB.
Altera Innovators Day 2025
Agilex FPGA development, system integration, AI tools and hands-on tutorials in San Jose.
Solving Power Puzzles in FPGA Design — The SmartPower Advantage
Power estimation and analysis during FPGA development.
Efinix and Future Electronics FPGA Workshop 2025 — Milpitas
Hands-on workshop covering Efinix tools, RISC-V demonstrations and Titanium devices.
Enabling New Space Innovation with Low-Power, Radiation-Tolerant Mil-Plastic FPGAs
Low-power FPGA choices for space applications.