MATLAB to AMD Vitis HLS workflow
Generating synthesizable C++ with HDL Coder in MATLAB R2025a.
FPGA events
Add event69 events
HeiChips Summer School 2025
Open-source chip design, programmable logic and a tapeout hackathon.
Performance pragmas in AMD Vitis HLS
Translating throughput targets into synthesis constraints.
FPGA Conference Europe 2025
Low-power FPGAs, edge AI and the Altera platform.
From ORs to Factory Floors – Intelligent 4K Vision at the Edge with Microchip FPGAs
Edge vision for medical and industrial systems.
Post-quantum security and FPGA field updates
Lattice seminar on CNSA 2.0, PQC algorithms, crypto agility and FPGA updates.
Real Time Edge Vision AI on FPGAs with VectorBlox SDK
INT8-optimized vision models on Microchip FPGA boards.
AMD Alveo V80: AVED and partner implementations
Reference design, low-latency AI inference and FPGA networking.
AMD Versal design tools and architecture: webinar series
Power, thermal design, NoC, transceivers, processors and embedded software.
FPGA Developers' Forum 2025
Implementation methods, tool flows and FPGA applications in physics and other engineering fields.