Timing closure for AMD Versal devices
A step-by-step flow for finding and resolving timing violations.
221 events
A step-by-step flow for finding and resolving timing violations.
Project configuration and a first application for the RISC-V soft processor.
PCIe Gen4, LPDDR5, transceivers, Ethernet and device security.
Seaside: FPGA architectures, CAD algorithms and high-level synthesis.
Algorithm–architecture co-design for data-science accelerators.
Deterministic vision pipelines using FPGA architectures.
Embedded software support for AMD adaptive SoCs and FPGAs.
FPGA architecture, AI acceleration and security.
SD-card boot, Linux tooling and software deployment for an autonomous Zynq/AD9361 radio platform.
Synchronising distributed radios using White Rabbit and FPGA clocking resources.