CameraLink on On-Board Computer- PolarFire SoC
Image acquisition with FPGA logic and a RISC-V processor subsystem.
FPGA events
Add event61 events
FPGA for AI acceleration
Design considerations for FPGA-based AI acceleration at the edge and in servers.
USB Extension Challenges in Professional Audio-Visual Environments
Protocol-aware USB transport over IP using FPGA hardware.
Deploying Deterministic Ethernet With TSN: A Complete 1G Endpoint Solution Using PolarFire SoC
A 1G TSN implementation for deterministic networking.
Timing closure for AMD Versal devices
A step-by-step flow for finding and resolving timing violations.
Zephyr RTOS on AMD MicroBlaze V
Project configuration and a first application for the RISC-V soft processor.
AMD Kintex UltraScale+ Gen 2 FPGA overview
PCIe Gen4, LPDDR5, transceivers, Ethernet and device security.
FPGA 2026
Seaside: FPGA architectures, CAD algorithms and high-level synthesis.
The Era of FPGA Acceleration
Algorithm–architecture co-design for data-science accelerators.
Every Millisecond Between Photon and Pixel Changes What We Can Build
Deterministic vision pipelines using FPGA architectures.