FPGA events

Topic: Verilog / SystemVerilog Clear all

20 events

May 26, 2026, 18:30–22:30 Russia · Saint PetersburgCompleted

YADRO FPGA community meetup 2026

Recording of the 26 May 2026 meetup: yosys-slang, SystemRDL, register documentation, Edge AI on FPGA and AI-assisted waveform analysis.

Hybrid Verilog / SystemVerilog Yosys

Apr 24 – 26, 2026 Russia · ZelenogradCompleted

YADRO SoC Design Challenge 2026

An offline student hackathon covers SoC physical design, UVM and system verification, RTL design, and DFT structures for RISC-V and modern microproces…

In person Verilog / SystemVerilog FPGA + SoC

Nov 29, 2025, 11:00–21:00 Russia · MoscowCompleted

FPGA-Systems 2025 with YADRO — Moscow

Recordings from both rooms of the 29 November 2025 conference: RTL, DSP, PCIe prototyping, FPGA-to-ASIC design, verification and physical implementati…

Hybrid Verilog / SystemVerilog FPGA + SoC

Apr 18 – 20, 2025 Russia · ZelenogradCompleted

YADRO SoC Design Challenge 2025

Archive of the 2025 YADRO and MIET engineering hackathon in Zelenograd: practical digital-design and verification tasks.

In person Verilog / SystemVerilog FPGA + SoC

Nov 30, 2024, 10:30–18:00 Russia · MoscowCompleted

FPGA-Systems 2024.02 × YADRO — Moscow

Programme, recording and slides from 30 November 2024: Chisel/Scala, UVM, RISC-V, verification, timing and HDMI on FPGA.

Hybrid Verilog / SystemVerilog FPGA + SoC

Oct 26, 2024, 11:00–18:00 Russia · Saint PetersburgCompleted

FPGA-Systems 2024.02 × YADRO — Saint Petersburg

Recording and slides from 26 October 2024: FPGA and ASIC physical design, embedded Linux, prototyping, PyUVM and Simtera.

Hybrid Verilog / SystemVerilog FPGA + SoC

Jun 1, 2024, 11:00–17:00 Russia · MoscowCompleted

FPGA-Systems 2024.1

The hybrid meetup covered SATA controllers, Simtera 4.0, Virtex-7 DRFM, AVC/H.264 hardware coding, industrial FPGA automation, and RISC-V on FPGA.

Hybrid Verilog / SystemVerilog FPGA + SoC

May 25, 2024, 11:00–17:00 Russia · Saint PetersburgCompleted

FPGA-Systems 2024.1

The hybrid meetup covered FPGA transceiver development, verification strategy, trusted OS boot, PyUVM, and verification-component libraries.

Hybrid Verilog / SystemVerilog FPGA + SoC

Apr 19 – 21, 2024 Russia · ZelenogradCompleted

YADRO SoC Design Challenge 2024

Archive of the 2024 YADRO and MIET engineering hackathon in Zelenograd: practical digital-design and verification tasks.

In person Verilog / SystemVerilog FPGA + SoC

Mar 2, 2024 Belarus · MinskCompleted

YADRO ASIC+RTL+FPGA MEETUP: from verification to test launch

A hybrid YADRO meetup covered SoC verification, iterative FPGA builds, automated test infrastructure, UVM, Cocotb, PyUVM and FPGA prototyping clusters…

Hybrid Verilog / SystemVerilog FPGA + SoC