Knowledge graphs for engineering agents: lessons from virtual commissioning
Researchers connect TIA Portal and NX MCD data in a knowledge graph and test agents on three virtual-commissioning tasks.
Audience and applicability
For engineers preparing FPGA integration reviews. The article proposes linking module ports, clock/reset domains and verification reports to source locations and project revisions; this adaptation has not been tested on FPGA.
The graph joins two engineering domains
Max Diekmann and colleagues extract PLC information from Siemens TIA Portal and kinematic metadata from NX MCD into a knowledge graph. A hierarchical agent framework uses that graph for system questions, simulation-component generation and cross-domain signal mapping. The evaluated outputs belong to a laboratory manufacturing system, not an FPGA implementation.
| Task class | Reported score% | What the task checks |
|---|---|---|
| UC1: system understanding | 90.7 | Mean correctness, grounding and completeness: 9 queries, 10 runs each |
| UC2: component generation | 100.0 | Executable journals without manual correction: 3 queries, 10 runs each |
| UC3: signal mapping | 100.0 | Hit@1 top-ranked mapping: 4 queries, 10 runs each |
Different task metrics, summarized by the authors for one system. They are not FPGA correctness rates, and the percentage alone does not describe scale or coverage.
Data sourceThe baseline without engineering data produced no usable outputs; a graph-grounded single agent performed less well. This supports studying grounded access and task decomposition together. It does not establish that adding more agents is sufficient when a required domain is missing. The authors retain engineer validation as a final step.
A possible adaptation for EDA
The following is an editorial proposal, not an author-reported FPGA result. A similar graph could connect module ports, clock/reset domains, interface contracts, constraints and verification reports. The graph would record where each relationship came from and which revision it applies to. An agent could retrieve those facts when preparing an integration review; it would still need the FPGA tools to establish implementation results.
- Choose one bounded task, such as finding width or clock-domain inconsistencies between two modules, and define the expected answer independently.
- Import structured declarations deterministically. Keep extracted facts separate from interpretations inferred from names or comments.
- Attach source locations and revision identifiers to edges; an old timing report must not certify changed RTL.
- Use failed or missing retrieval as an explicit result. Validate a proposed connection with the relevant simulation, formal or implementation check.
Coverage and reproducibility limits
The reported limits include incomplete source metadata, ambiguous names, unsupported component templates and large graph queries exhausting memory. Broad requests had to be decomposed. Validation on one laboratory system does not establish portability to other machines or FPGA tools.
This review uses arXiv v1 from 2 June 2026; no later version was listed at the check date. A public code/data package for this specific framework was not established. The arXiv distribution license is not a general permission to reuse the source figures, so the illustration here is original. FPGA.camp has not reproduced the agents or the laboratory experiment.