LLM ladder-logic translation: preserve structure, then verify behavior
A Rockwell-to-Siemens PLC example preserves project hierarchy better than branch logic, exposing the limits of schema-constrained translation.
Audience and applicability
For engineers reviewing AI-assisted migration tools. The PLC example helps separate document structure, instruction semantics and behavioral verification when considering a similar approach for HDL projects.
A translator with an intermediate representation
Oluwatosin Ogundare, Promise Ekpo and Nathanial Wiggins study conversion of Rockwell L5X ladder-logic projects into Siemens SimaticXML. Their pipeline extracts XML structure, builds a hierarchical intermediate representation, constrains generated output to a target schema and validates it. An LLM translates descriptions of logic; deterministic processing preserves explicitly represented project relationships.
The useful boundary is between information captured in that representation and information the model must infer. Tasks, programs and routines are explicit. Branch topology is harder to recover from the source format, and the evaluation reflects that difference. The paper also compares generated XML representations using cosine similarity; similarity is not a proof that two controllers produce the same state transitions.
One shift-register example
| Category | Correct / total | Correct% |
|---|---|---|
| Task / program / routine hierarchy | 11 / 11 | 100.0 |
| Rungs → target networks | 58 / 64 | 90.6 |
| Bracketed branch logic | 35 / 41 | 85.4 |
| Arithmetic and comparisons | 89 / 96 | 92.7 |
| Data movement and state coils | 69 / 78 | 88.5 |
| Scope tags and global variables | 134 / 147 | 91.2 |
| Overall | 396 / 437 | 90.6 |
Author-reported translation assessment for one program. These percentages are not behavioral-equivalence scores or industrial deployment success rates.
Data sourceThe authors present this as validation of a translation architecture, not comprehensive coverage of PLC constructs. A correctly imported hierarchy can still contain a wrong condition, retained state or branch. The totals include partially correct and failed translations, so the headline hierarchy score should not stand in for the whole result.
A possible HDL adaptation
The paper does not translate HDL or implement an FPGA. The following is an editorial proposal: use a typed intermediate representation to keep widths, signedness, state and interface relationships explicit during an AI-assisted HDL migration. Require the model to report unsupported constructs rather than silently invent replacements.
- Separate syntax/schema validation from simulation or equivalence checking; record both results.
- Include boundary values and stateful sequences in the behavioral comparison, not only a successful target-tool import.
- Preserve source-to-target mappings so an engineer can locate a failed branch or state update.
- Check implementation constraints and timing on the intended FPGA after validating the translated behavior.
What is available
This review uses arXiv v1, submitted on 29 May 2026, under CC BY 4.0. No later version was listed at the check date. The paper says raw files are available from the corresponding author on request; a public code/data package was not established. Without those inputs, a broad reproducibility or vendor-compatibility claim would go beyond the demonstrated example. FPGA.camp has not repeated the translation experiment.