conceptbeginnerconfidence 4/5CC BY 4.0

From HDL to bitstream

The practical FPGA flow is lint/simulation, synthesis, constraints, place-and-route, timing, bitstream, programming and board validation.

Keep each flow artifact reproducible: source HDL, constraints, project scripts, generated reports and exact tool versions. GUI-only flows are acceptable for learning, but production projects should be scriptable.

Graph links

Boards: icebreaker/icebreaker, digilent/arty-a7, sipeed/tang-nano-20k

Chips: none

Toolchains: yosys, nextpnr, vivado-webpack, quartus-prime

Protocols: none

Pitfalls: Skipping simulation shifts basic bugs into the slowest debug loop: hardware bring-up.

Related boards

SipeedGW2A/GW2ARbeginnerconfidence 4/5

Tang Nano 20K

Compact Gowin GW2AR board with HDMI, audio amplifier, TF card slot, SDRAM, and onboard debugger.

GW2AR-LV18QN88C8/I7open toolchain28.17 USDeducationvideoaudiorisc-v

iCEBreaker FPGAiCE40 UltraPlusbeginnerconfidence 4/5

iCEBreaker

Open-source educational Lattice iCE40UP5K board designed around the Yosys, nextpnr and IceStorm flow.

iCE40UP5K-SG48open toolchainprice unknowneducationcontroldspformal

DigilentArtix-7beginnerconfidence 4/5

Arty A7

Digilent Artix-7 board with Vivado WebPACK support, Pmods, Arduino/chipKIT style expansion, DDR3 and Ethernet.

XC7A35TICSG324-1Lprice unknowneducationrisc-vcontroldsp

Sources

https://yosyshq.readthedocs.io/projects/yosys/en/latest/https://github.com/YosysHQ/nextpnr https://docs.amd.com/

Suggest correction