Digilent Artix-7 board with Vivado WebPACK support, Pmods, Arduino/chipKIT style expansion, DDR3 and Ethernet.
Short verdict: beginner learning. Critical characteristics must be checked against sources before purchase or external wiring.
Ethernet x1, USB UART x1, USB-JTAG x1
Pmod x4, Arduino/chipKIT shield x1
DDR3 variant-specific; verify in Digilent memory tab
An FPGA is configurable digital logic: the design becomes hardware structure after synthesis, place-and-route and bitstream generation.
Pick the first board by toolchain access, verified examples, documentation, community help and a realistic first project.
Constraint files bind logical ports to package pins and define clocks, I/O standards and timing assumptions.
The practical FPGA flow is lint/simulation, synthesis, constraints, place-and-route, timing, bitstream, programming and board validation.
Vivado is AMD's FPGA design suite for modern Xilinx/AMD FPGA and SoC families.
Start from Digilent's resource center, select the exact 35T or 100T variant, import constraints and run a simple Vivado design.
FPGA order codes encode family, density, package, speed grade, temperature range and sometimes feature variants.
UART is the simplest board-visible debug channel, but it still needs clock-derived baud timing, synchronizers and a testbench.
Pmod is a small expansion connector ecosystem; verify voltage, pin mapping and peripheral protocol before attaching modules.
A RISC-V softcore project needs enough logic, memory, a debug path, firmware build flow and a board-specific memory/IO map.
Do not copy constraints or resource assumptions between variants without checking the exact FPGA part and reference files.
