project_templateintermediateconfidence 4/5CC BY 4.0

RISC-V softcore on FPGA

A RISC-V softcore project needs enough logic, memory, a debug path, firmware build flow and a board-specific memory/IO map.

Start with UART firmware output before adding caches, SDRAM or Linux. For Linux-capable systems, choose a board with documented external memory and an existing SoC example.

Graph links

Boards: sipeed/tang-nano-20k, radiona/ulx3s, digilent/arty-a7, terasic/de10-nano

Chips: none

Toolchains: yosys-nextpnr-trellis, vivado-webpack, gowin-eda

Protocols: uart, spi, wishbone, axi

Pitfalls: CPU demos fail silently when clock, reset or memory initialization are wrong.

Related boards

SipeedGW2A/GW2ARbeginnerconfidence 4/5

Tang Nano 20K

Compact Gowin GW2AR board with HDMI, audio amplifier, TF card slot, SDRAM, and onboard debugger.

GW2AR-LV18QN88C8/I7open toolchain28.17 USDeducationvideoaudiorisc-v

Radiona / EMARDECP5intermediateconfidence 3/5

ULX3S

Open-hardware Lattice ECP5 board used for open-source FPGA development, education, LiteX and retro-computing projects.

LFE5U-85F-6BG381Copen toolchainprice unknowneducationvideoretrorisc-v

DigilentArtix-7beginnerconfidence 4/5

Arty A7

Digilent Artix-7 board with Vivado WebPACK support, Pmods, Arduino/chipKIT style expansion, DDR3 and Ethernet.

XC7A35TICSG324-1Lprice unknowneducationrisc-vcontroldsp

TerasicCyclone V SoCintermediateconfidence 3/5

DE10-Nano

Terasic Cyclone V SoC board widely used for Intel FPGA education, Linux-on-SoC labs and MiSTer-style retro FPGA work.

5CSEBA6U23I7price unknowneducationlinuxretrorisc-v

Sources

https://github.com/YosysHQ/picorv32 https://github.com/enjoy-digital/litex

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