protocol_notebeginnerconfidence 4/5CC BY 4.0

UART in FPGA projects

UART is the simplest board-visible debug channel, but it still needs clock-derived baud timing, synchronizers and a testbench.

A UART echo is a good second project after blink. It forces clock math, serial timing, RX synchronization and a repeatable board-visible result.

Graph links

Boards: sipeed/tang-nano-20k, digilent/arty-a7, icebreaker/icebreaker

Chips: none

Toolchains: none

Protocols: uart

Pitfalls: Wrong clock frequency gives wrong baud rate. RX input must cross safely into the local clock domain.

SipeedGW2A/GW2ARbeginnerconfidence 4/5

Compact Gowin GW2AR board with HDMI, audio amplifier, TF card slot, SDRAM, and onboard debugger.

GW2AR-LV18QN88C8/I7open toolchain28.17 USDeducationvideoaudiorisc-v

iCEBreaker FPGAiCE40 UltraPlusbeginnerconfidence 4/5

Open-source educational Lattice iCE40UP5K board designed around the Yosys, nextpnr and IceStorm flow.

iCE40UP5K-SG48open toolchainprice unknowneducationcontroldspformal

DigilentArtix-7beginnerconfidence 4/5

Digilent Artix-7 board with Vivado WebPACK support, Pmods, Arduino/chipKIT style expansion, DDR3 and Ethernet.

XC7A35TICSG324-1Lprice unknowneducationrisc-vcontroldsp