tutorialbeginnerconfidence 4/5CC BY 4.0
Verilog simulation: minimal path
A minimal simulation has a DUT, testbench, clock/reset generation, stimulus, assertions or checks, and waveform capture only when needed.
Start with a small self-checking testbench. Generate a clock, release reset, apply stimulus and make the test fail on wrong output. Use waveforms for diagnosis, not as the only acceptance criterion.