Efinix announces Sapphire RV64, a 64-bit RISC-V soft SoC for its FPGAs
Efinix announced Sapphire RV64 on 28 September 2026: a configurable 64-bit RISC-V core with an optional SV39 MMU for Linux and DDR3, LPDDR4x and HyperRAM support for Titanium, Topaz and Trion FPGAs.
Summary
Efinix announced the 64-bit Sapphire RV64 RISC-V soft SoC for Titanium, Topaz and Trion FPGAs on 28 September 2026.
Overview
On 28 September 2026 Efinix announced the Sapphire RV64 SoC, a 64-bit RISC-V processor core that extends the existing 32-bit Sapphire SoC suite. The press release positions it for applications that have outgrown the performance, addressable memory, cache and I/O limits of 32-bit embedded cores.
According to the press release, the core uses a seven-stage pipeline implementing RISC-V64IM with optional A, F, D, C, Zba, Zbb, Zbs and Zicbom extensions, 4 to 512 KB of on-chip RAM, a multi-way L1 cache, an optional L2 cache, a branch predictor and pre-fetchers. An optional SV39 memory management unit provides Linux support.
The support page adds that the SoC is configurable with one to four 64-bit processors, a clock from 20 to 400 MHz limited by the fMAX of the design, and a memory controller for DDR3, LPDDR4x or HyperRAM modules from 4 MB to 8 GB. Efinix describes the core as similar to the open-source VexiiRiscv, optimized for Trion and Titanium FPGAs.
Efinix names availability for all Titanium and Topaz FPGAs and for Trion devices; the exact Trion list is worded differently across its pages, so confirm the device in the datasheet. Cores are configured in the Efinity IP Manager and software is built in the Eclipse-based Efinity RISC-V Embedded Software IDE.
The support page also publishes resource and fMAX tables for Efinity 2026.1. For the single-core Basic L2 configuration, Titanium Ti375 C529 shows 14,258 logic/adders, 12,624 flip-flops, 188 memory blocks, 17 DSP blocks and 278 MHz; Trion T120 F324 shows 77 MHz. These are vendor figures for named configurations and depend on the device.
Verified facts
Announcement date and product: Efinix announced Sapphire RV64 SoC on 28 September 2026. Source: https://www.efinixinc.com/company-pr-efinix-brings-64-bit-riscv-performance-to-embeddded-fpga-designs-with-new-sapphire-rv64-soc.html. Checked: 2026-10-02. Confidence: 5/5.
ISA and pipeline: seven stages, RISC-V64IM, optional A, F, D, C, Zba, Zbb, Zbs and Zicbom. Source: https://www.efinixinc.com/company-pr-efinix-brings-64-bit-riscv-performance-to-embeddded-fpga-designs-with-new-sapphire-rv64-soc.html. Checked: 2026-10-02. Confidence: 5/5.
Linux support depends on the optional SV39 MMU; memory controller supports DDR3, HyperRAM and LPDDR4x at up to 3,200 Mbps. Source: https://www.efinixinc.com/company-pr-efinix-brings-64-bit-riscv-performance-to-embeddded-fpga-designs-with-new-sapphire-rv64-soc.html. Checked: 2026-10-02. Confidence: 5/5.
Clock is configurable from 20 to 400 MHz, the real limit is the design fMAX; module sizes from 4 MB to 8 GB are listed. Source: https://www.efinixinc.com/support/ip/riscv-sapphire-rv64.php. Checked: 2026-10-02. Confidence: 5/5.
The support page calls the core similar to the open-source VexiiRiscv, optimized for Trion and Titanium FPGAs. Source: https://www.efinixinc.com/support/ip/riscv-sapphire-rv64.php. Checked: 2026-10-02. Confidence: 5/5.
Resource and fMAX tables are vendor figures for named configurations on named devices (Efinity 2026.1). They depend on the device and configuration. Source: https://www.efinixinc.com/support/ip/riscv-sapphire-rv64.php. Checked: 2026-10-02. Confidence: 5/5.
Supported device lists for Trion differ between the press release, the support page and the products page. Source: https://www.efinixinc.com/products-riscv.html. Checked: 2026-10-02. Confidence: 4/5.
Engineering benefit
An optional SV39 MMU and module sizes up to 8 GB give the core a route to Linux and to memory spaces beyond 32-bit cores, according to Efinix. Optional features; the sources give no Linux boot demonstration. Source: https://www.efinixinc.com/company-pr-efinix-brings-64-bit-riscv-performance-to-embeddded-fpga-designs-with-new-sapphire-rv64-soc.html. Checked: 2026-10-02. Confidence: 4/5.
An optional custom instruction interface with 1,024 IDs lets designers attach FPGA logic to the instruction stream. Source: https://www.efinixinc.com/support/ip/riscv-sapphire-rv64.php. Checked: 2026-10-02. Confidence: 4/5.
Standard RISC-V debug and co-debug with the FPGA debugger are listed in the features. Source: https://www.efinixinc.com/support/ip/riscv-sapphire-rv64.php. Checked: 2026-10-02. Confidence: 4/5.
Commercial benefit
Efinix states that customers of the 32-bit Sapphire SoCs can scale up without re-architecting their systems (CTO statement). Vendor statement; no migration case is published. Price and licence terms are not stated. Source: https://www.efinixinc.com/company-pr-efinix-brings-64-bit-riscv-performance-to-embeddded-fpga-designs-with-new-sapphire-rv64-soc.html. Checked: 2026-10-02. Confidence: 3/5.
One core is offered across Titanium, Topaz and Trion families, so a design can target several device classes of one vendor. Exact Trion device list differs between Efinix pages. Source: https://www.efinixinc.com/company-pr-efinix-brings-64-bit-riscv-performance-to-embeddded-fpga-designs-with-new-sapphire-rv64-soc.html. Checked: 2026-10-02. Confidence: 4/5.
Community benefit
Because Efinix calls the core similar to the open-source VexiiRiscv, public VexiiRiscv material may help engineers understand the architecture (editorial inference). Similar does not mean identical; Sapphire RV64 itself is configured through Efinity, not built from the VexiiRiscv repository. Source: https://www.efinixinc.com/support/ip/riscv-sapphire-rv64.php. Checked: 2026-10-02. Confidence: 3/5.
Critical review
The Trion device list differs: the press release says T20 and above, the support page says all except T4, the products page says all except T4 and T8. Check the exact device in the datasheet. Source: https://www.efinixinc.com/support/ip/riscv-sapphire-rv64.php. Checked: 2026-10-02. Confidence: 4/5.
The clock can be set up to 400 MHz, but the published fMAX values are 77 MHz and 65 MHz on Trion T120 and 250 to 278 MHz on Titanium Ti375 in the listed configurations. Source: https://www.efinixinc.com/support/ip/riscv-sapphire-rv64.php. Checked: 2026-10-02. Confidence: 5/5.
No CoreMark, DMIPS or Linux boot result is given in the collected sources; "Linux support" means an optional MMU. Source: https://www.efinixinc.com/company-pr-efinix-brings-64-bit-riscv-performance-to-embeddded-fpga-designs-with-new-sapphire-rv64-soc.html. Checked: 2026-10-02. Confidence: 4/5.
The core is configured and built in Efinity for Efinix devices; licence and price terms are not stated on the collected pages. Source: https://www.efinixinc.com/support/ip/riscv-sapphire-rv64.php. Checked: 2026-10-02. Confidence: 4/5.
The Ti375 and Tz170 tables list identical logic, flip-flop, memory block and DSP counts and differ only in fMAX; treat the tables as indicative and confirm in the datasheet. Source: https://www.efinixinc.com/support/ip/riscv-sapphire-rv64.php. Checked: 2026-10-02. Confidence: 4/5.
The support page gives configuration-by-configuration tables with the Efinity version, so the figures are reproducible in principle. Source: https://www.efinixinc.com/support/ip/riscv-sapphire-rv64.php. Checked: 2026-10-02. Confidence: 4/5.
The datasheet and user guide are linked from the vendor support page. Source: https://www.efinixinc.com/support/ip/riscv-sapphire-rv64.php. Checked: 2026-10-02. Confidence: 5/5.
Practical recommendations
Before planning Linux on this core, read the datasheet for your exact device and memory controller, and treat the 400 MHz slider as a wish and the fMAX column as the contract.
Run your own build in Efinity with the target device and report the fMAX, resources and Efinity version next to any claim you repeat.
Official links
Efinix press release (28 Sep 2026)
Sapphire RV64 SoC support page
Evidence
On 28 September 2026 Efinix announced the Sapphire RV64 SoC, a 64-bit RISC-V processor core that expands the Sapphire SoC suite. Source: https://www.efinixinc.com/company-pr-efinix-brings-64-bit-riscv-performance-to-embeddded-fpga-designs-with-new-sapphire-rv64-soc.html. Checked: 2026-10-02.
Sapphire RV64 uses a seven-stage pipeline implementing the RISC-V64IM ISA with optional A, F, D, C, Zba, Zbb, Zbs and Zicbom extensions. Source: https://www.efinixinc.com/company-pr-efinix-brings-64-bit-riscv-performance-to-embeddded-fpga-designs-with-new-sapphire-rv64-soc.html. Checked: 2026-10-02.
The press release lists 4 to 512 KB of on-chip RAM, a multi-way L1 instruction and data cache, an optional L2 cache, a branch predictor and hardware and software pre-fetchers. Source: https://www.efinixinc.com/company-pr-efinix-brings-64-bit-riscv-performance-to-embeddded-fpga-designs-with-new-sapphire-rv64-soc.html. Checked: 2026-10-02.
Linux support is provided by an optional SV39 memory management unit. Source: https://www.efinixinc.com/company-pr-efinix-brings-64-bit-riscv-performance-to-embeddded-fpga-designs-with-new-sapphire-rv64-soc.html. Checked: 2026-10-02.
The memory controller supports DDR3, HyperRAM and LPDDR4x operation at up to 3,200 Mbps. Source: https://www.efinixinc.com/company-pr-efinix-brings-64-bit-riscv-performance-to-embeddded-fpga-designs-with-new-sapphire-rv64-soc.html. Checked: 2026-10-02.
The support page describes a configurable, cached soft RISC-V SoC with 1 to 4 64-bit processors and a configurable operating frequency of 20 to 400 MHz, limited by the fMAX of the design. Source: https://www.efinixinc.com/support/ip/riscv-sapphire-rv64.php. Checked: 2026-10-02.
The support page states that the core is similar to the open-source VexiiRiscv but optimized for Trion and Titanium FPGAs. Source: https://www.efinixinc.com/support/ip/riscv-sapphire-rv64.php. Checked: 2026-10-02.
The support page lists support for memory module sizes from 4 MB to 8 GB and an external memory interface of one half-duplex AXI3 or one full-duplex AXI4 port up to 512 bits. Source: https://www.efinixinc.com/support/ip/riscv-sapphire-rv64.php. Checked: 2026-10-02.
The press release states availability for all Titanium FPGAs, all Topaz FPGAs and all Trion devices (T20 and above). Source: https://www.efinixinc.com/company-pr-efinix-brings-64-bit-riscv-performance-to-embeddded-fpga-designs-with-new-sapphire-rv64-soc.html. Checked: 2026-10-02.
The Efinix support page lists support for all Trion FPGAs except the T4 and all Titanium FPGAs, and the products page lists all Trion FPGAs except the T4 and T8, Titanium and Topaz FPGAs. Source: https://www.efinixinc.com/support/ip/riscv-sapphire-rv64.php. Checked: 2026-10-02.
Sapphire cores are configured through the Efinity IP Manager, built with the Efinity IDE, and developed with the Eclipse-based Efinity RISC-V Embedded Software IDE. Source: https://www.efinixinc.com/company-pr-efinix-brings-64-bit-riscv-performance-to-embeddded-fpga-designs-with-new-sapphire-rv64-soc.html. Checked: 2026-10-02.
For the Titanium Ti375 C529 Basic L2 configuration (Efinity 2026.1) the support page lists 14,258 logic/adders, 12,624 flip-flops, 188 memory blocks, 17 DSP blocks and 278 MHz fMAX; for Trion T120 F324 Basic L2 it lists 77 MHz fMAX. Source: https://www.efinixinc.com/support/ip/riscv-sapphire-rv64.php. Checked: 2026-10-02.
The support page lists an optional custom instruction interface with 1,024 IDs and debug support following the standard RISC-V debug specification with up to 4 hardware breakpoints and co-debug with the FPGA debugger. Source: https://www.efinixinc.com/support/ip/riscv-sapphire-rv64.php. Checked: 2026-10-02.