Orthogone launches ultra-low-latency FPGA IP portfolio with encrypted RTL
Orthogone released a licensed Ethernet MAC/PCS, TCP/UDP offload and PCIe DMA IP kit for AMD UltraScale+ and Versal. RTL is delivered encrypted; no prices or latency figures in the release.
Overview
On 30 September 2026 Orthogone Technologies (Montreal) announced availability of its Ultra-Low-Latency (ULL) FPGA IP Portfolio for AMD UltraScale+ and Versal platforms. The kit combines Ethernet MAC/PCS at 1G, 10G, 25G, 40G and 100G (optional RS-FEC at 25G and 100G), TCP/IP and UDP/IP Offload Engines, and a PCIe Gen3/Gen4 circular-buffer DMA controller.
The RTL is delivered encrypted. Together with the encrypted source the kit includes reference designs for AMD Alveo boards, simulation testbenches, a Linux driver stack and documentation. Access requires a commercial license (project, site, corporate, annualized or card-based); the release names no prices.
The release itself gives no latency figures, only the phrase "sub-microsecond-class". Figures with measurement conditions are published on Orthogone product pages: for example 17.1 ns round trip for 10G MAC/PCS, 196 ns / 399 ns for 100G without / with RS-FEC, and 585 ns minimum round trip for the PCIe DMA controller. Measurement points differ between these numbers, so they cannot be compared with each other directly.
Orthogone says the IP came from FinTech and has early users in aerospace and defense and in quantum computing. These are vendor statements; the release names no customers and cites no independent tests.
Verified facts
Release dated 30 September 2026 (Montreal) announces availability for UltraScale+ and Versal. Source: https://www.prnewswire.com/news-releases/orthogone-technologies-launches-ultra-low-latency-fpga-ip-portfolio-for-multi-industry-deterministic-networking-302893290.html. Checked: 2026-10-02. Confidence: 5/5.
The release states that RTL is delivered encrypted and lists project, site, corporate, annualized and card-based licensing. Source: https://www.prnewswire.com/news-releases/orthogone-technologies-launches-ultra-low-latency-fpga-ip-portfolio-for-multi-industry-deterministic-networking-302893290.html. Checked: 2026-10-02. Confidence: 5/5.
The release gives "sub-microsecond-class" without figures; numeric values come only from Orthogone product pages with stated conditions. Source: https://orthogone.com/ultra-low-latency-ethernet-mac/. Checked: 2026-10-02. Confidence: 5/5.
Engineering benefit
The kit covers MAC/PCS, Layer 2-4 offload and host DMA in one set, with testbenches, reference designs for Alveo and a Linux driver stack, which reduces the protocol logic a team has to write itself. Benefit as described by the vendor; no independent integration report. Source: https://www.prnewswire.com/news-releases/orthogone-technologies-launches-ultra-low-latency-fpga-ip-portfolio-for-multi-industry-deterministic-networking-302893290.html. Checked: 2026-10-02. Confidence: 4/5.
Product pages publish latency and resource figures with stated conditions (device family, speed grade, measurement points), for example 10G MAC/PCS at 1.4k LUTs and 1.1k FFs for the 16-bit variant. Vendor measurements; conditions differ between rows. Source: https://orthogone.com/ultra-low-latency-ethernet-mac/. Checked: 2026-10-02. Confidence: 4/5.
Commercial benefit
Five licensing models (project, site, corporate, annualized, per-card) let a team match the license to a single project or a product line; a free 30-day evaluation is offered on the product page. No prices are published, so total cost cannot be estimated from public sources. Source: https://www.prnewswire.com/news-releases/orthogone-technologies-launches-ultra-low-latency-fpga-ip-portfolio-for-multi-industry-deterministic-networking-302893290.html. Checked: 2026-10-02. Confidence: 4/5.
Community benefit
The vendor positions the kit for teams outside FinTech: data center and HPC, aerospace and defense, industrial and robotics, medical, communications, test and measurement, quantum computing. Community benefit is indirect: the RTL is closed, no public repository or community channel is announced. Source: https://www.prnewswire.com/news-releases/orthogone-technologies-launches-ultra-low-latency-fpga-ip-portfolio-for-multi-industry-deterministic-networking-302893290.html. Checked: 2026-10-02. Confidence: 3/5.
Critical review
The release gives no latency numbers; the product pages give numbers measured at different points (for example 17.1 ns vs 34.1 ns for the same 10G MAC/PCS depending on AXI width and CDC), so one headline figure would mislead. Source: https://orthogone.com/ultra-low-latency-ethernet-mac/. Checked: 2026-10-02. Confidence: 5/5.
RTL is encrypted: a team cannot audit, patch or port the source, and debugging in simulation depends on vendor-provided models and support. This is an editorial inference from the delivery format stated in the release. Source: https://www.prnewswire.com/news-releases/orthogone-technologies-launches-ultra-low-latency-fpga-ip-portfolio-for-multi-industry-deterministic-networking-302893290.html. Checked: 2026-10-02. Confidence: 4/5.
The Orthogone page also lists a 25G result on Stratix-10, while the release names only AMD UltraScale+ and Versal; platform scope should be confirmed with the vendor before planning a non-AMD design. Source: https://orthogone.com/ultra-low-latency-ethernet-mac/. Checked: 2026-10-02. Confidence: 4/5.
Claims such as "proven in production for several years" and "best-in-class latency" are vendor statements; no customer or third-party benchmark is cited. Source: https://www.prnewswire.com/news-releases/orthogone-technologies-launches-ultra-low-latency-fpga-ip-portfolio-for-multi-industry-deterministic-networking-302893290.html. Checked: 2026-10-02. Confidence: 4/5.
The vendor labels all figures as representative examples under specific conditions and publishes those conditions, which makes them reproducible in principle on the same hardware. Source: https://www.prnewswire.com/news-releases/orthogone-technologies-launches-ultra-low-latency-fpga-ip-portfolio-for-multi-industry-deterministic-networking-302893290.html. Checked: 2026-10-02. Confidence: 4/5.
A free 30-day evaluation lets a team verify latency and resources on its own board before buying. Source: https://orthogone.com/ultra-low-latency-ethernet-mac/. Checked: 2026-10-02. Confidence: 4/5.
Practical recommendations
Ask for a latency number together with its measurement points (TxSoP to RxSoF or RxSoP, transceiver included or not, CDC included or not) and for the speed grade; repeat the measurement on your board during the 30-day evaluation.
Ask whether simulation of encrypted RTL works in your simulator and how fixes are delivered; closed RTL protects the vendor secret, and the bug should not hide behind the same wrapper.
Official links
ULL Ethernet MAC/PCS and portfolio page
Evidence
On 30 September 2026 Orthogone Technologies announced availability of its Ultra-Low-Latency (ULL) FPGA IP Portfolio for AMD UltraScale+ and Versal adaptive platforms, available now for evaluation and licensing. Source: https://www.prnewswire.com/news-releases/orthogone-technologies-launches-ultra-low-latency-fpga-ip-portfolio-for-multi-industry-deterministic-networking-302893290.html. Checked: 2026-10-02.
The portfolio packages Ethernet MAC/PCS with optional Reed-Solomon FEC, hardware TCP/IP and UDP/IP offload engines and a PCIe circular-buffer DMA controller; MAC/PCS covers IEEE 802.3 at 1G, 10G, 25G, 40G and 100G with optional RS-FEC at 25G and 100G. Source: https://www.prnewswire.com/news-releases/orthogone-technologies-launches-ultra-low-latency-fpga-ip-portfolio-for-multi-industry-deterministic-networking-302893290.html. Checked: 2026-10-02.
The offload engines move Layer 2 through Layer 4 processing into FPGA logic; the PCIe circular-buffer DMA controller moves data between host and FPGA over PCIe Gen3/Gen4. Source: https://www.prnewswire.com/news-releases/orthogone-technologies-launches-ultra-low-latency-fpga-ip-portfolio-for-multi-industry-deterministic-networking-302893290.html. Checked: 2026-10-02.
The kit ships with encrypted RTL source, reference designs for AMD Alveo boards, end-to-end simulation testbenches, a Linux driver stack and documentation; licensing options are project, site, corporate, annualized and card-based. No prices are stated. Source: https://www.prnewswire.com/news-releases/orthogone-technologies-launches-ultra-low-latency-fpga-ip-portfolio-for-multi-industry-deterministic-networking-302893290.html. Checked: 2026-10-02.
The release describes latency only as "sub-microsecond-class" and states that performance figures are representative examples measured under specific conditions. Source: https://www.prnewswire.com/news-releases/orthogone-technologies-launches-ultra-low-latency-fpga-ip-portfolio-for-multi-industry-deterministic-networking-302893290.html. Checked: 2026-10-02.
The vendor says the technology originated in FinTech, was deployed in production and supported for several years, and has early adopters outside FinTech, including aerospace and defense and quantum computing (vendor statement). Source: https://www.prnewswire.com/news-releases/orthogone-technologies-launches-ultra-low-latency-fpga-ip-portfolio-for-multi-industry-deterministic-networking-302893290.html. Checked: 2026-10-02.
Orthogone product page: 10G Ethernet MAC/PCS wire-to-wire round-trip latency 17.1 ns (16-bit GTY, 16-bit AXI-4 Stream, UltraScale+, GTY + MAC/PCS, serial loopback, TxSoP to RxSoF). Source: https://orthogone.com/ultra-low-latency-ethernet-mac/. Checked: 2026-10-02.
Orthogone product page: 100G MAC/PCS wire-to-wire round-trip latency 196 ns with RS-FEC off and 399 ns with RS-FEC on (UltraScale+, mid speed grade -2, transceiver + PCS + MAC, Tx + Rx). Source: https://orthogone.com/ultra-low-latency-ethernet-mac/. Checked: 2026-10-02.
Orthogone PCIe DMA page: minimum round-trip time as low as 585 ns (PCIe Gen4 x8 lanes, AMD x3522pv, Intel Core i9-14900KS host, synchronous AXI-4 interfaces 512b at 250 MHz, payload counts 128k); 608 ns and 635 ns on two other host systems. Source: https://orthogone.com/ultra-low-latency-ethernet-mac/high-speed-data-transfer-smartnics-host-cpu-pcie-dma-controller/. Checked: 2026-10-02.
Orthogone TCP/UDP page: 6.2 ns Tx and 6.2 ns Rx processing latency in cut-through mode on the AMD x3522pv platform; up to 64 connections per endpoint. Source: https://orthogone.com/ultra-low-latency-ethernet-mac/10g-tcp-udp-ip-core/. Checked: 2026-10-02.
Orthogone product page offers a free 30-day product evaluation on request. Source: https://orthogone.com/ultra-low-latency-ethernet-mac/. Checked: 2026-10-02.