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Verilator: SystemVerilog simulator and lint
April 25, 2026· GitHub open-source· Guide
Verilator compiles Verilog/SystemVerilog into C++/SystemC and is used in regression flows.
Open-sourceVerilatorVerilog / SystemVerilog
The card is a reference for simulation and lint materials in the projects section.
Checked by FPGA.camp editors on 2026-04-26.