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Yosys 0.69: synthesis changes and a Verific option

September 27, 2026· Yosys releases· Digest

Yosys 0.69 removes several synthesis passes and adds a SystemVerilog 2023 option to its Verific integration.

Summary

Yosys 0.69 removes several synthesis passes and adds a SystemVerilog 2023 option to its Verific integration.

Overview

Release 0.69 drops synthesis flows for CoolRunner2 and GreenPAK4 along with nlutmap. It also removes several synthesis flags and the logger option for controlling stderr.

The Verific integration gains -sv2023 for SystemVerilog 2023. This release note describes the integration-specific option.

Original source
Yosys 0.69: synthesis changes and a Verific option | FPGA.camp