LiteEth
Checked on GitHubModern Ethernet core comparison point.
Interfaces and peripheralsMigen/Python/VerilogNo license foundM2 · Simulation-testedupdated 2 days ago
Interfaces and peripherals
22 cores. Check the license and tests before integration.
LitePCIe
Checked on GitHubOpen PCIe ecosystem core.
Interfaces and peripheralsMigen/Python/VerilogNo license foundM2 · Simulation-testedupdated 3 days ago
Modern adaptation of OpenCores UART16550.
Interfaces and peripheralsNo license foundM1 · Prototype
Common GitHub UART implementation.
Interfaces and peripheralsNo license foundM1 · Prototype
Ethernet candidate with OpenCores ethmac relation.
Interfaces and peripheralsNo license foundM1 · Prototype
Common SPI/SPI flash block in LiteX designs.
Interfaces and peripheralsMigen/Python/VerilogNo license foundM1 · Prototype
OpenTitan UART documentation.
Interfaces and peripheralsNo license foundM0 · Idea
LiteX complex link core.
Interfaces and peripheralsNo license foundM1 · Prototype
I2C reference with docs.
Interfaces and peripheralsNo license foundM0 · Idea
SPI device reference.
Interfaces and peripheralsNo license foundM0 · Idea
Ethernet MAC/UDP/IP stack candidate.
Interfaces and peripheralsNo license foundM1 · Prototype
I2C core alternative.
Interfaces and peripheralsNo license foundM1 · Prototype
SPI core alternative.
Interfaces and peripheralsNo license foundM1 · Prototype
PWM category seed.
Interfaces and peripheralsVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
Small SPI alternative.
Interfaces and peripheralsVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
Canonical UART reference and common FuseSoC adaptations.
Interfaces and peripheralsVerilogNo license foundM1 · Prototype
Important comparison point for LiteEth and IObundle Ethernet.
Interfaces and peripheralsVerilogNo license foundM1 · Prototype
Common small peripheral for beginner/professional comparison.
Interfaces and peripheralsVerilogNo license foundM1 · Prototype
Common reusable peripheral baseline.
Interfaces and peripheralsVerilogNo license foundM1 · Prototype
PCIe endpoint/DMA candidate.
Interfaces and peripheralsNo license foundM1 · Prototype
CAN/LIN category seed.
Interfaces and peripheralsVerilog/VHDL unknown until reviewNo license foundM1 · Prototype
USB category seed.
Interfaces and peripheralsVerilog/VHDL unknown until reviewNo license foundM1 · Prototype