Requires independent simulation, synthesis, timing, board and license review before production use.
colibri
CERN's library of common RTL components in VHDL-2008: memories, I/O, clock domain crossing, stream interfaces. Licence CERN-OHL-W-2.0.
Buses and infrastructureVHDL-2008CERN-OHL-W-2.0M1 · Prototype
Worth knowing
Facts
The source is not on GitHub — an editor checks tests and license manually.
- Maturity
- M1 · Prototype
- License
- CERN-OHL-W-2.0 · Copyleft
- Tests
- not found
- CI
- not found
- Formal verification
- not found
- FuseSoC
- not found
Source exists, but no tests were found. How maturity is assigned
Purpose
Library of common RTL components in VHDL-2008 (memories, I/O, clock domain crossing, stream interfaces, encoders) for FPGA projects, vendor-independent.
UARTSPII2CJTAGAvalon-STAXI4-StreamWishbone B4Aurora 64b/66bAvalon-STAXI4-StreamWishbone B4VivadoQuartusFuseSoCHogGHDLSymbiYosysNVCVUnit
Boards
No one has confirmed a board run yet.
Add evidenceSources
- The colibri repository on GitLab is described as 'Vendor-Independent, Fully Verified, Open Source VHDL Common Library'. · 2026-10-02
- README: colibri is a collection of common components, functions and procedures used in CERN gateware projects; code is i… · 2026-10-02
- README: the content of the repository is licensed under CERN-OHL-W-2.0 if another licence is not specified; colibri.core… · 2026-10-02
- README lists modules: common, comms, endec, fileio, interfaces, io, memory, misc, pipes, packet, proto; testbenches are… · 2026-10-02
- memory module: fifo, cc_fifo, cc_ram_fifo, packet FIFOs, bicam, rom, ram, simple_dpram, simple_dpram_be, true_dpram, rin… · 2026-10-02
- io module: i2c_controller (master), uart, uart_rx, uart_tx, spi_master, spi_slave, jtag_serdes. · 2026-10-02
- interfaces module: Avalon-ST CDC, FIFO and width converter, Avalon-ST to AXI Stream and back, Avalon-ST RAM readers and… · 2026-10-02
- common module: counter, comparator, clock domain crossing circuits (synchro, synchro_reset, synchro_pulse, synchro_hands… · 2026-10-02
- fv/README: formal verification uses SBY (SymbiYosys) with the ghdl Yosys plugin; the GitLab CI simulation job uses the n… · 2026-10-02
- Module readmes mark every listed entity with simulation and self-checking testbench; formal verification is marked for o… · 2026-10-02
- changelog.md lists Release 2026.07 and Release 2026.05. · 2026-10-02
- CERN newsletter of 18 September 2026 announces the public release; more than 100 RTL components in pure VHDL-2008; used… · 2026-10-02
How to check it locally
- Try a synthesis smoke run with: Vivado, Quartus, FuseSoC, Hog, GHDL, SymbiYosys, NVC, VUnit.
Scores and how they are computed
License, tests, CI, formal checks, documentation and activity come from the repository check. Usefulness and learning value are editorial estimates.
Quality36
Verification15
License55
Docs35
Integration55
Usefulness0
Beginner0
Professional26
Confidence40
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