OpenTitan prim library
Checked on GitHubPrimitive library reference.
Buses and infrastructureApache-2.0M4 · Production-readyupdated today
Cores
Open HDL cores for FPGA. License, tests and activity checked on GitHub.
wb_intercon
Checked on GitHubCommon Wishbone interconnect package.
Buses and infrastructureISCM2 · Simulation-testedupdated 7 months ago
verilog-axi
Checked on GitHubAXI component library and comparison source.
Buses and infrastructureMITM2 · Simulation-testedupdated 2 years ago
verilog-axis
Checked on GitHubAXI-Stream component library.
Buses and infrastructureMITM2 · Simulation-testedupdated 2 years ago
stream_utils
Checked on GitHubStream FIFO/width conversion baseline.
Buses and infrastructureISCM2 · Simulation-testedupdated 12 months ago
taxi
Checked on GitHubSuccessor ecosystem for AXI/stream components.
Buses and infrastructureCERN-OHL-S-2.0M2 · Simulation-testedupdated 34 days ago
CERN's library of common RTL components in VHDL-2008: memories, I/O, clock domain crossing, stream interfaces. Licence CERN-OHL-W-2.0.
Buses and infrastructureVHDL-2008CERN-OHL-W-2.0M1 · Prototype
pulp-platform common_cells
Checked on GitHubReusable cells widely used by PULP projects.
Buses and infrastructureSystemVerilogNo license foundM4 · Production-readyupdated 14 days ago
ZipCPU wb2axip
Checked on GitHubWishbone/AXI bridge and formal property library.
Buses and infrastructureVerilogNo license foundM2 · Simulation-testedupdated 21 days ago
Open Logic AXI/base/intf
Checked on GitHubFuseSoC-listed open logic package family.
Buses and infrastructureNo license foundM4 · Production-readyupdated 4 days ago
pulp-platform axi
Checked on GitHubAXI components and infrastructure.
Buses and infrastructureSystemVerilogNo license foundM4 · Production-readyupdated 8 days ago
BaseJump STL
Checked on GitHubReusable SystemVerilog library.
Buses and infrastructureNo license foundM2 · Simulation-testedupdated 4 days ago
CDC helpers for composition planner.
Buses and infrastructureNo license foundM1 · Prototype
GPIO reference with register docs.
Buses and infrastructureNo license foundM1 · Prototype
GPIO category seed.
Buses and infrastructureVerilog/VHDL unknown until reviewNo license foundM1 · Prototype