Comparison helps you see quickly which core carries less license, review, and integration risk.
Raw PDM RX core на Verilog-2001 для MEMS microphones: генерирует PDM clock, сэмплирует 1-битный поток и выдаёт valid/ready stream. Не выполняет PDM-to-PCM decimation.
Source is available, but commercial use may require a separate license.
The core does not include a decimator/CIC/FIR pipeline.
Шаблон production-style FPGA IP: manifest, registry, board/toolchain scaffolding, SPDX checks, separated licenses and release checklist.
This is a template/example, not a standalone core.
Generated projects require separate review.
| Signal | AccelFury af-pdm-rx | AccelFury core-template |
|---|---|---|
| Category / source | audio / sensor interface / PDM RX github | generator / template / IP methodology github |
| Review / maturity | Manually reviewed M4-M5 candidate | Manually reviewed M2-M3 template |
| License | AccelFury Source AvailableManual review required | CERN-OHL-S-2.0 + AGPL + CC-BY-SAManual review required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | Synthesized for targetLikely compatible | unknown |
| Tests / CI / formal | Tests: NoCI: NoFormal: No | Tests: NoCI: NoFormal: No |
| Docs / FuseSoC / board demo | Docs: NoFuseSoC: NoBoard demo: Yes | Docs: YesFuseSoC: NoBoard demo: No |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | PDMunknown | unknownunknown |
| Toolchains | Verilator | Verilator |
| Warnings |
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