Decision matrix

How to read the matrixStart with review status, license clarity, and warnings. If records are close, then look at tests, board evidence, and toolchain fit.2/4

AccelFury af-pdm-rx

M4-M5 candidateMaturity levelMaturity M4-M5 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.

Raw PDM RX core на Verilog-2001 для MEMS microphones: генерирует PDM clock, сэмплирует 1-битный поток и выдаёт valid/ready stream. Не выполняет PDM-to-PCM decimation.

githubManually reviewedAccelFury Source Available
Critical

Source is available, but commercial use may require a separate license.

Info

The core does not include a decimator/CIC/FIR pipeline.

OpenCores WBScope

M5 candidateMaturity levelMaturity M5 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.

Useful Wishbone-accessible debug core by ZipCPU author.

opencoresAuto indexedGPL
Warning

Manual review is required.

SignalAccelFury af-pdm-rxOpenCores WBScope
Category / sourceaudio / sensor interface / PDM RX
github
verification/logic analyzer
opencores
Review / maturity
Manually reviewedM4-M5 candidateMaturity levelMaturity M4-M5 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
Auto indexedM5 candidateMaturity levelMaturity M5 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale.
License
AccelFury Source Availableunknown_or_manual_review_required
GPLunknown_or_manual_review_required
Evidence / boards
EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees.
EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees.
Board status
Board statusBoard status: Synthesized for target. Synthesis is confirmed, but this is not a hardware run.Board statusBoard status: Likely compatible. Likely compatibility still needs local verification.
unknown
Tests / CI / formal
TestsCurrent metadata does not show reproducible test evidence yet.CICurrent metadata does not show confirmed CI yet.FormalFormal evidence has not been found yet.
TestsCurrent metadata does not show reproducible test evidence yet.CICurrent metadata does not show confirmed CI yet.FormalFormal evidence has not been found yet.
Docs / FuseSoC / board demo
DocsDocumentation is not evidence-confirmed yet.FuseSoCFuseSoC packaging has not been found yet.Board demoBoard-level demo or target evidence is visible.
DocsDocumentation is not evidence-confirmed yet.FuseSoCFuseSoC packaging has not been found yet.Board demoBoard-level demo or target evidence is not confirmed yet.
Signals
QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification
QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification
Interfaces / buses
PDMunknown
JTAG/debugWishbone
ToolchainsVerilatorVerilator
Warnings
  • Source is available, but commercial use may require a separate license.
  • The core does not include a decimator/CIC/FIR pipeline.
  • Confirmed board evidence with a real microphone is still missing.
  • Check clock/reset handling and constraints before integration.
  • Manual review is required.