Comparison helps you see quickly which core carries less license, review, and integration risk.
Шаблон production-style FPGA IP: manifest, registry, board/toolchain scaffolding, SPDX checks, separated licenses and release checklist.
This is a template/example, not a standalone core.
Generated projects require separate review.
Canonical UART reference and common FuseSoC adaptations.
The license requires manual review.
The source appears stale or legacy.
| Signal | AccelFury core-template | OpenCores UART16550 |
|---|---|---|
| Category / source | generator / template / IP methodology github | peripheral/UART opencores |
| Review / maturity | Manually reviewed M2-M3 template | Auto indexed M1-M3 candidate |
| License | CERN-OHL-S-2.0 + AGPL + CC-BY-SAManual review required | unknown until checkedManual review required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | Tests: NoCI: NoFormal: No | Tests: NoCI: NoFormal: No |
| Docs / FuseSoC / board demo | Docs: YesFuseSoC: NoBoard demo: No | Docs: YesFuseSoC: YesBoard demo: No |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | unknownunknown | UARTunknown |
| Toolchains | Verilator | FuseSoC, Verilator |
| Warnings |
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