fifo
M1-M3 candidateGeneric FIFO baseline.
githubAuto indexedunknown
The license requires manual review.
Comparison helps you see quickly which core carries less license, review, and integration risk.
Generic FIFO baseline.
The license requires manual review.
Canonical UART reference and common FuseSoC adaptations.
The license requires manual review.
The source appears stale or legacy.
| Signal | fifo | OpenCores UART16550 |
|---|---|---|
| Category / source | memory/FIFO github | peripheral/UART opencores |
| Review / maturity | Auto indexed M1-M3 candidate | Auto indexed M1-M3 candidate |
| License | unknownUnknown | unknown until checkedManual review required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | Tests: NoCI: NoFormal: No | Tests: NoCI: NoFormal: No |
| Docs / FuseSoC / board demo | Docs: NoFuseSoC: NoBoard demo: No | Docs: YesFuseSoC: YesBoard demo: No |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | FIFO/stream, Memoryunknown | UARTunknown |
| Toolchains | unknown | FuseSoC, Verilator |
| Warnings |
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