Comparison helps you see quickly which core carries less license, review, and integration risk.
Open PCIe ecosystem core.
The license requires manual review.
There is a vendor tooling or license constraint.
Canonical UART reference and common FuseSoC adaptations.
The license requires manual review.
The source appears stale or legacy.
| Signal | LitePCIe | OpenCores UART16550 |
|---|---|---|
| Category / source | peripheral/PCIe github | peripheral/UART opencores |
| Review / maturity | Auto indexedM1-M3 candidateMaturity levelMaturity M1-M3 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale. | Auto indexedM1-M3 candidateMaturity levelMaturity M1-M3 candidate: evidence-gated readiness label. No source cannot exceed M0; no synthesis evidence cannot reach M4; no board evidence cannot reach M5. Open the KB guide for the full scale. |
| License | unknownunknown_or_manual_review_required | unknown until checkedunknown_or_manual_review_required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | TestsCurrent metadata does not show reproducible test evidence yet.CICI or a similar automated check is visible in current metadata.FormalFormal evidence has not been found yet. | TestsCurrent metadata does not show reproducible test evidence yet.CICurrent metadata does not show confirmed CI yet.FormalFormal evidence has not been found yet. |
| Docs / FuseSoC / board demo | DocsDocumentation is not evidence-confirmed yet.FuseSoCFuseSoC packaging has not been found yet.Board demoBoard-level demo or target evidence is not confirmed yet. | DocsDocumentation is visible in current metadata.FuseSoCA FuseSoC .core file or compatible packaging is visible.Board demoBoard-level demo or target evidence is not confirmed yet. |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | PCIeunknown | UARTunknown |
| Toolchains | LiteX, Verilator | FuseSoC, Verilator |
| Warnings |
|
|
