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Up to four cores side by side: maturity, license, tests and activity.

AttributeNEORV32VexiiRiscvSERV
MaturityM4 · Production-readyM2 · Simulation-testedM4 · Production-ready
LicenseBSD-3-Clause · Commercial-friendlyMIT · Commercial-friendlyISC · Commercial-friendly
LanguageVHDLSpinalHDL (Scala)Verilog
Testsyesyesyes
CIyesyesyes
Formal———
FuseSoC——yes
Activityupdated 5 days agoupdated 4 days agoupdated 38 days ago
Boards———
Interfaces—AXI4, Wishbone, Tilelink, AXI4, Wishbone, Tilelink—
CategoryCPUs and computeCPUs and computeCPUs and compute

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