VexiiRiscv

Worth knowing

Facts

From GitHub data, checked October 2, 2026.

Maturity

M2 · Simulation-tested

License

MIT · Commercial-friendly

Tests

yes

CI

yes

Formal verification

not found

FuseSoC

not found

Last commit

updated 4 days ago

Stars

255

The repository contains tests or a testbench. How maturity is assigned

Purpose

Open-source configurable RISC-V core (RV32/64) from SpinalHDL, successor of VexRiscv, with optional MMU and Linux support.

Boards

No one has confirmed a board run yet.

Sources

• VexiiRiscv (Vex2Risc5) is the successor of VexRiscv; the README says it is work in progress. · 2026-10-02
• The README lists RV32/64 I[M][A][F][D][C][S][U][B], in-order execution with single or dual issue, BTB, GShare and RAS br… · 2026-10-02
• The README states that it can run Linux, Buildroot and Debian and shows a demonstration of a quad-core VexiiRiscv runnin… · 2026-10-02
• The README lists AXI4, Wishbone and Tilelink memory buses and notes that RVA is not available in some configurations. · 2026-10-02
• The README states up to 5.24 CoreMark/MHz and 2.50 Dhrystone/MHz without naming the configuration. · 2026-10-02
• The README says that after generation a file named VexiiRiscv.v appears in the repository root and that FPGA board pin c… · 2026-10-02
• The LICENSE file is the MIT License, Copyright (c) 2023 SpinalHDL. · 2026-10-02
• The documentation introduction says VexiiRiscv follows the RISC-V ISA, covers in-order designs from small microcontrolle… · 2026-10-02
• The documentation (https://spinalhdl.github.io/VexiiRiscv-RTD/ redirects to the master version) has a framework section… · 2026-10-02
• Efinix writes on the Sapphire RV64 SoC support page that the core is similar to the open-source VexiiRiscv, optimized fo… · 2026-10-02