OpenCores UART16550
M1-M3 candidateCanonical UART reference and common FuseSoC adaptations.
opencoresAuto indexedunknown until checked
The license requires manual review.
The source appears stale or legacy.
/cores
Core comparison
Comparison helps you see quickly which core carries less license, review, and integration risk.
Decision matrix
How to read the matrixStart with review status, license clarity, and warnings. If records are close, then look at tests, board evidence, and toolchain fit.2/4OpenTitan IP blocks
M1-M3 candidateHigh-quality IP block library with docs and verification culture.
githubAuto indexedApache-2.0
Manual review is required.
| Signal | OpenCores UART16550 | OpenTitan IP blocks |
|---|---|---|
| Category / source | peripheral/UART opencores | security/root-of-trust/IP blocks github |
| Review / maturity | Auto indexed M1-M3 candidate | Auto indexed M1-M3 candidate |
| License | unknown until checkedManual review required | Apache-2.0Manual review required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | Tests: NoCI: NoFormal: No | Tests: YesCI: NoFormal: No |
| Docs / FuseSoC / board demo | Docs: YesFuseSoC: YesBoard demo: No | Docs: NoFuseSoC: NoBoard demo: No |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | UARTunknown | unknownunknown |
| Toolchains | FuseSoC, Verilator | Verilator |
| Warnings |
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