OpenCores WDSP
M1-M3 candidateExample of DSP cores with Wishbone and claimed FPGA evidence.
opencoresAuto indexedLGPL
The source appears stale or legacy.
Comparison helps you see quickly which core carries less license, review, and integration risk.
Example of DSP cores with Wishbone and claimed FPGA evidence.
The source appears stale or legacy.
Small open RISC-V CPU used by OpenTitan.
Manual review is required.
| Signal | OpenCores WDSP | Ibex |
|---|---|---|
| Category / source | DSP/FIR/IIR/FFT opencores | processor/RISC-V github |
| Review / maturity | Auto indexed M1-M3 candidate | Auto indexed M7 candidate |
| License | LGPLManual review required | Apache-2.0Manual review required |
| Evidence / boards | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. | EvidencePublic evidence links attached to this record.BoardsBoard-linked compatibility records, not portability guarantees. |
| Board status | unknown | unknown |
| Tests / CI / formal | Tests: NoCI: NoFormal: No | Tests: NoCI: NoFormal: No |
| Docs / FuseSoC / board demo | Docs: NoFuseSoC: NoBoard demo: No | Docs: NoFuseSoC: NoBoard demo: No |
| Signals | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification | QualityQualityUsefulnessUsefulnessIntegrationIntegrationVerificationVerification |
| Interfaces / buses | unknownWishbone | unknownunknown |
| Toolchains | GHDL | Verilator |
| Warnings |
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