High-quality IP block library with docs and verification culture.
Auto indexedApache-2.0
/cores
Core comparison
Comparison helps you see quickly which core carries less license, review, and integration risk.
Pick 2–4 cores
How to build a shortlistEnter comma-separated slugs or add the cards below. Compare only keeps unique slugs and a maximum of four records.Ibex
P0Small open RISC-V CPU used by OpenTitan.
Auto indexedApache-2.0
LiteX
P0Central open SoC builder and integration framework.
Auto indexedBSD-2-Clause-like until checked
Шаблон production-style FPGA IP: manifest, registry, board/toolchain scaffolding, SPDX checks, separated licenses and release checklist.
Manually reviewedCERN-OHL-S-2.0 + AGPL + CC-BY-SA
Bus protocol reference for OpenCores-era reusable IP.
Auto indexedpublic-domain-like per OpenCores WISHBONE page
Useful Wishbone-accessible debug core by ZipCPU author.
Auto indexedGPL
Canonical UART reference and common FuseSoC adaptations.
Auto indexedunknown until checked
Industrial-grade open RISC-V core family source.
Auto indexedSolderpad
P0Auto indexedgithub
OpenTitan IP blocks
security/root-of-trust/IP blocks
High-quality IP block library with docs and verification culture.
LicenseApache-2.0Lower commercial risk
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use72
Int52
Ver40
SystemVerilogApache-2.0unknown
Manual review is required.
P0Auto indexedgithub
Ibex
processor/RISC-V
Small open RISC-V CPU used by OpenTitan.
LicenseApache-2.0Lower commercial risk
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use72
Int52
Ver40
SystemVerilogApache-2.0unknown
Manual review is required.
P0Auto indexedgithub
LiteX
SoC builder/generator
Central open SoC builder and integration framework.
LicenseBSD-2-Clause-like until checkedLower commercial risk
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use72
Int52
Ver40
Migen/Python/VerilogBSD-2-Clause-like until checkedMemory
Manual review is required.
P2Manually reviewedgithub
AccelFury core-template
generator / template / IP methodology
Шаблон production-style FPGA IP: manifest, registry, board/toolchain scaffolding, SPDX checks, separated licenses and release checklist.
LicenseCERN-OHL-S-2.0 + AGPL + CC-BY-SALicense needs review
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q42
Use36
Int70
Ver18
Rust/SystemVerilog/TypeScriptCERN-OHL-S-2.0 + AGPL + CC-BY-SAunknown
This is a template/example, not a standalone core.
Generated projects require separate review.
P0Auto indexedopencores
OpenCores Wishbone
bus/Wishbone
Bus protocol reference for OpenCores-era reusable IP.
Licensepublic-domain-like per OpenCores WISHBONE pageLicense needs review
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use54
Int52
Ver18
Specificationpublic-domain-like per OpenCores WISHBONE pageunknownWishbone
Manual review is required.
P0Auto indexedopencores
OpenCores WBScope
verification/logic analyzer
Useful Wishbone-accessible debug core by ZipCPU author.
LicenseGPLLicense needs review
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use72
Int52
Ver40
VerilogGPLJTAG/debugWishbone
Manual review is required.
P0Auto indexedopencores
OpenCores UART16550
peripheral/UART
Canonical UART reference and common FuseSoC adaptations.
Licenseunknown until checkedLicense needs review
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q48
Use72
Int76
Ver22
Verilogunknown until checkedUART
The license requires manual review.
The source appears stale or legacy.
P0Auto indexedgithub
OpenHW CORE-V cores
processor/RISC-V
Industrial-grade open RISC-V core family source.
LicenseSolderpadLicense needs review
EvidencePublic evidence links attached to this record.
BoardsBoard-linked compatibility records, not portability guarantees.
ConfidenceHow strongly the current record is backed by reviewed evidence.
Q54
Use72
Int52
Ver40
SystemVerilogSolderpadunknown
Manual review is required.